Spatial Accelerator Architecture for Low Power Embedded Applications
Video
Team Information
Team Members
Thomas Repetti, PhD Candidate, Computer Science, Columbia Engineering
Martha Kim, Associate Professor of Computer Science, Columbia University
Joao Cerqueira, PhD Alumnus, Electrical Engineering, Columbia University
Mingoo Seok, Associate Professor, Electrical Engineering, Columbia Engineering
Abstract
Embedded systems typically rely on specialized ASIC accelerator hardware to meet demanding performance and power targets. While optimal for their designed purpose, the inherent lack of flexibility and engineering cost overheads motivate field programmable solutions, the most widely deployed of which area FPGAs. FPGAs suffer from their own drawbacks, however, in terms of performance and efficiency degradation as well as being an unintuitive target for software developers and still requiring considerable hardware expertise to use. We present a prototype for a compiler-targetable low power spatial accelerator that approaches ASIC performance on a variety of workloads while maintaining a familiar programming interface.
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Team Contact: Thomas Repetti (use form to send email)
